
Datasheet as PDF
Technical Datasheet as PDF

The POWERLINK Enhanced Ethernet MAC Controller (PE²MAC) developed by port is a special MAC controller optimized for Ethernet POWERLINK for FPGAs.
Through several special transmit buffers and the possibility to respond automatically to POWERLINK frames by hardware, extremely short response times are reached. Special receive filters allow pre-filtering of POWERLINK messages by the MAC controller and releases the software from this tasks. These filters support the pre-selection of Ethernet frames, that are needed by the processing software. Based on the used settings only those frames that match the filters are stored in the receive buffers. This mechanism releases the CPU from processing frames not relevant for the software.
For
the MAC unit a VHDL firmware design was developed that is
optimized for POWERLINK data transfer.
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With FPGAs custom-made, scalable and future-proof solutions open up for the equipment manufacturer. The reusability of IPs, quick time to market and high cost efficiency, are substantial advantages of a FPGA based solution. E.g. a solution with Industrial Ethernet interface, hub logic and processor core can be implemented in one single XILINX-FPGA. Furthermore the embedded processor can directly be implemented in the FPGA.
The PE²MAC from port works in a Xilinx-FPGA and is available with three different processor interfaces:
The PE²MAC is a standalone component that is linked to the processor via registers (control- and status information), a dual-port-memory (data buffer) and an interrupt request signal. Furthermore a separated signal is provided that signals an incoming SoC packet.
A special PE²MAC driver provides an optimal interconnection to port’s POWERLINK Library.

In connection with the POWERLINK-HUB not only a straightforward connection to an POWERLINK network is provided but also a sophisticated solution with technical parameters (short response times, fast reaction to network events) that conforms to the requirements of the POWERLINK standard is available.

platform
Xilinx-FPGA
processor-connection
OPB, PLB v4.6 or SRAM
operation mode
100MBit
PHY interface
MII
Slices
1083 - 1238
FFs
952 - 1295
LUTs
1975 - 2161
BRAMs
6
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1712/00
PE清AC-XIL-OPB-VHDL
1712/01
PE清AC-XIL-PLB-VHDL 1712/02
PE清AC-XIL-SRAM-VHDL
1712/50
PE清AC-XIL-OPB-NETL
1712/51
PE清AC-XIL-PLB-NETL 1712/52
PE清AC-XIL-SRAM-NETL
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Datasheet as PDF
Technical Datasheet as PDF
$Revision: 1.6 $